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ISL6529, ISL6529A
Data Sheet April 12, 2005 FN9070.5
Dual Regulator-Synchronous Rectified Buck PWM and Linear Power Controllers
The ISL6529, ISL6529A provide the power control and protection for two output voltages in high-performance graphics cards and other embedded processor applications. The dual-output controllers drive two N-Channel MOSFETs in a synchronous rectified buck converter topology and one N-Channel MOSFET in a linear configuration. The ISL6529, ISL6529A provide both a regulated high current, low voltage supply and an independent, lower current supply integrated in a 14-lead SOIC package. The controllers are ideal for graphic card applications where regulation of both the graphics processing unit (GPU) and memory supplies is required. The synchronous rectified buck converters incorporate simple, single feedback loop, voltage-mode control with fast transient response. Both the switching regulator and linear regulator provide a maximum static regulation tolerance of 2% over line, load, and temperature ranges. Each output is user-adjustable by means of external resistors. An integrated soft-start feature brings both supplies into regulation in a controlled manner. Each output is monitored via the FB pins for undervoltage events. If either output drops below 51.5% of the nominal output level, both converters are shut down.
Features
* Provides two regulated voltages - One synchronous rectified buck PWM controller - One linear controller * Both controllers drive low cost N-Channel MOSFETs * 12V direct drive saves external components * Small converter size - 600kHz constant frequency operation - Small external component count * Excellent output voltage regulation - Both outputs: 1% over temperature - ISL6529AC - Both outputs: 2% over temperature - ISL6529C * 5V down conversion * PWM and linear output voltage range: down to 0.8V * Simple single-loop voltage-mode PWM control design * Fast PWM converter transient response - High-bandwidth error amplifier - Full 0-100% duty ratio * Linear controller drives N-Channel MOSFET pass transistor * Fully-adjustable outputs * Undervoltage fault monitoring on both outputs * QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile * Pb-Free Available (RoHS Compliant)
Ordering Information
PART NUMBER* ISL6529ACB ISL6529ACBZ (Note) ISL6529ACR ISL6529ACRZ (Note) ISL6529CB ISL6529CBZ (Note) ISL6529CR ISL6529CRZ (Note) ISL6529EVAL1 TEMP. RANGE (C) 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 PACKAGE 14 Ld SOIC PKG. DWG. # M14.15
14 Ld SOIC (Pb-free) M14.15 16 Ld 5x5 QFN 16 Ld 5x5 QFN (Pb-free) 14 Ld SOIC L16.5x5B L16.5x5B M14.15
Applications
* Graphics-GPU and memory supplies * ASIC power supplies * Embedded processor and I/O supplies * DSP supplies
14 Ld SOIC (Pb-free) M14.15 16 Ld 5x5 QFN 16 Ld 5x5 QFN (Pb-free) L16.5x5B L16.5x5B
Related Literature
* Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)
Evaluation Board
*Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002-2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6529, ISL6529A Pinouts
ISL6529, ISL6529A (SOIC) TOP VIEW
LGATE 1 PGND 2 GND 3 5VCC 4 DRIVE2 5 FB2 6 NC 7 14 UGATE 13 12VCC 12 NC 11 NC 10 COMP 9 FB 8 NC PGND GND 5VCC DRIVE2 NC = NO INTERNAL CONNECTION 5 FB2 6 NC 7 NC 8 NC 1 2 3 4 12 11 10 9 12VCC NC COMP FB
ISL6529, ISL6529A (QFN) TOP VIEW
UGATE 14 LGATE
NC
16
15
13
NC = NO INTERNAL CONNECTION
2
NC
FN9070.5 April 12, 2005
Block Diagram
5VCC
0.80V
0.41V
1.28V
3
VOLTAGE REFERENCE POWER-ON RESET (POR)
ISL6529, ISL6529A
SHUTDOWN FB2 12VCC SOFTSTART AND FAULT LOGIC
RESTART
12VCC
+5V
DRIVE2
UGATE
EA2 INHIBIT SOFT-START +5VCC EA1 COMP1 OSCILLATOR PGND LGATE PWM
INHIBIT SOFT-START
GATE LOGIC
GND
UV1 UV2 FB COMP
FN9070.5 April 12, 2005
ISL6529, ISL6529A Simplified Power System Diagram
+VIN +12V +5V
Q1 Q3 VOUT2 + LINEAR CONTROLLER VOUT1 PWM CONTROLLER Q2 +
ISL6529 ISL6529A
Typical Application
+VIN (+5V or +3.3V) +12V +5V CBP 5VCC CBP 12VCC
CIN Q3 VOUT2 2.5V + FB2 DRIVE2
+
UGATE
Q1 LOUT PHASE
VOUT1 1.5V +
COUT2
ISL6529 ISL6529A
LGATE
Q2
COUT1
FB COMP
GND
PGND
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Absolute Maximum Ratings
UGATE, LGATE, DRIVE2,. . . . . . . . . . . . . . . GND - 0.3V to 12VCC 5VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V 12VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V FB, FB2, COMP, . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 4kV
Thermal Information
Thermal Resistance JA (C/W) JC (C/W) SOIC Package (Note 1) . . . . . . . . . . . . 68 NA QFN Package (Notes 2, 3). . . . . . . . . . 36 5 Maximum Junction Temperature (Plastic Package) . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C (SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage on 5VCC . . . . . . . . . . . . . . . . . . . . . . . . . +5V 10% Supply Voltage on 12VCC . . . . . . . . . . . . . . . . . . . . . . . +12V 10% Supply Voltage to drain of Upper MOSFETs . . . +3.3V to +5V 10% Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0C to 70C Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0C to 125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER VCC SUPPLY CURRENT Nominal Supply Current 12VCC Nominal Supply Current 5VCC POWER-ON RESET Rising 5VCC Threshold Falling 5VCCThreshold Rising 12VCC Threshold Falling 12VCCThreshold
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ICC ICC
UGATE, LGATE and DRIVE2 Open UGATE, LGATE and DRIVE2 Open
-
2.7 3.5
3.0 4.5
mA mA
12VCC = 12V 12VCC = 12V 5VCC = 5V 5VCC = 5V
4.25 3.75 9.6 9.3
4.4 3.82 10.3 9.6
4.5 4.0 10.8 10.2
V V V V
OSCILLATOR AND SOFT-START Free Running Frequency Ramp Amplitude Soft-Start Interval REFERENCE VOLTAGE Reference Voltage System Accuracy VREF ISL6529C ISL6529AC PWM CONTROLLER ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate FB Input Current COMP High Output Voltage COMP Low Output Voltage COMP High Output, Source Current GBWP SR II VOUT High VOUT Low IOUT High RL = 10K, CL = 10pF RL = 10K, CL = 10pF RL = 10K, CL = 10pF VFB = 0.8V 3.0 -2.5 80 15 6 20 4.5 0.5 -6.8 150 1.0 dB MHz V/s nA V V mA -2.0 -1.0 0.800 +2.0 +1.0 V % % FOSC DVOSC TSS 550 3.1 600 1.5 3.45 650 3.75 kHz VP-P ms
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Electrical Specifications
PARAMETER COMP Low Output, Sink Current Undervoltage Level (VFB/VREF) PWM CONTROLLER GATE DRIVERS UGATE and LGATE Maximum Voltage UGATE and LGATE Minimum Voltage UGATE and LGATE Source Current UGATE and LGATE Sink Current UGATE and LGATE OUTPUT IMPEDANCE LINEAR REGULATOR (DRIVE2) DC Gain Gain-Bandwidth Product Slew Rate FB2 Input Current Drive2 High Output Voltage Drive2 Low Output Voltage Drive2 High Output Source Current Drive2 Low Output Sink Current Over-Voltage Level (VFB2/VREF) Under-Voltage Level (VFB2/VREF) REGULATOR ISOLATION Change in Linear Regulator Output Voltage (Note 4) Change in PWM Regulator Output Voltage
(Note 4)
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic (Continued) SYMBOL IOUT Low VUV TEST CONDITIONS MIN 2.5 TYP 3.5 51.5 MAX UNITS mA %
VHGATE VLGATE IGATE IGATE RDS(on)
12VCC = 12V 12VCC = 12V 12VCC = 12V 12VCC = 12V 12VCC = 12V
11 -
12 0 -1 1 3.1
0.5 4.3
V V A A
RL = 10K, CL = 10pF GBWP SR II VOUT High VOUT Low IOUT High IOUT Low VOV VUV Percent of Nominal Percent of Nominal RL = 10K, CL = 10pF RL = 10K, CL = 10pF VFB2 = 0.8V
9.5 -0.7 0.85 -
80 15 6 20 10.3 0.1 -1.4 1.2 160 51.5
150 1.0 -
dB MHz V/s nA V V mA mA % %
Vout Vout
Linear Output = 2.5V, 6A Load Change on PWM PWM Output = 1.5V, 1A Load Change on Linear
-
<0.5 <0.5
-
% %
NOTE: 4. Measured in the evaluation board.
Functional Pin Descriptions
LGATE 1 PGND 2 GND 3 5VCC 4 DRIVE2 5 FB2 6 NC 7 14 UGATE 13 12VCC 12 NC 11 NC 10 COMP 9 FB 8 NC NC = NO INTERNAL CONNECTION
GND (Pin 3), (Pin 2 QFN)
Signal ground for the IC. All voltage levels are measured with respect to this pin. Place via close to pin to minimize impedance path to ground plane.
5VCC (Pin 4), (Pin 3 QFN)
Provide a well decoupled 5V bias supply for the IC to this pin. The voltage at this pin is monitored for Power-On Reset (POR) purposes.
DRIVE2 (Pin 5), (Pin 4 QFN)
Connect this pin to the gate terminal of an external N-Channel MOSFET transistor. This pin provides the gate voltage for the linear regulator pass transistor. It also provides a means of compensating the error amplifier for applications where the user needs to optimize the regulator transient response.
LGATE (Pin 1), (Pin 16 QFN)
Lower gate drive output. Connect to gate of the low-side MOSFET.
PGND (Pin 2), (Pin 1 QFN)
This pin is the power ground return for the lower gate driver.
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FB2 (Pin 6), (Pin 5 QFN)
Connect the output of the linear regulator to this pin through a properly sized resistor divider. The voltage at this pin is regulated to 0.8V. This pin is also monitored for undervoltage events. Pulling and holding FB2 above 1.28V shuts down both regulators. Releasing FB2 initiates soft-start on both regulators.
Soft-Start
The POR function initiates the digital soft-start sequence. Both the linear regulator error amplifier and PWM error amplifier reference inputs are forced to track a voltage level proportional to the soft-start voltage. As the soft-start voltage slews up, the PWM comparator regulates the output relative to the tracked soft-start voltage, slowly charging the output capacitor(s). Simultaneously, the linear output follows the smooth ramp of the soft-start function into normal regulation. Figure 1 shows the soft-start sequence of an ISL6529 evaluation board powered by an ATX supply. Note the uniform linear output voltage rise of the two ISL6529 output voltages. Once the voltage on 5VCC crosses the POR thresholds, both outputs begin their soft-start sequence. The triangle waveform from the PWM oscillator is compared to the rising error amplifier output voltage. As the error amplifier voltage increases, the pulse-width on the PWM increases to reach its steady-state duty cycle. The error amplifier reference of the linear controller also rises relative to the soft-start reference. Figure 2 shows the controlled stepped output voltage rise and associated charging current of a 390F polymer capacitor. By providing many small steps of current that effectively charge the output capacitor, the potentially large peak current resulting from a sudden, uncontrolled voltage rise is eliminated. The clock for the DAC producing the 30mV steps is approximately 18.5kHz, so there is a 18.5kHz ripple current component that lasts for the approximate 2.8ms start-up interval. A few clock cycles are used for initialization to insure that soft-start begins near zero volts.
NC (Pins 7, 8, 11, and 12), (Pins 6, 7, 8, 11, 13 and 15 QFN)
No internal connection.
FB (Pin 9), (Pin 9 QFN) and COMP (Pin 10), (Pin 10 QFN)
FB and COMP are the available external pins of the error amplifier. The FB pin is the inverting input of the error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the voltage-mode control feedback loop of the standard synchronous rectified buck converter.
12VCC(Pin 13), (Pin 12 QFN)
Provides bias voltage for the gate drivers.The voltage at this pin is monitored for Power-On Reset (POR) purposes.
UGATE (Pin 14), (Pin 14 QFN)
Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the MOSFET.
Description
Operation Overview
The ISL6529 monitors and precisely controls two output voltage levels. Refer to the Block Diagram, Simplified Power System Diagram, and Typical Application Schematic on pp. 2-3. The controller is intended for use in graphics cards or embedded processor applications with 5V and 12V bias input available. The IC integrates both a standard buck PWM controller and a linear controller. The PWM controller is designed to regulate the high current GPU voltage (VOUT1). The PWM controller regulates the output voltage to a level programmed by a resistor divider. The linear controller is designed to regulate the lower current local memory voltage (VOUT2) through an external N-Channel MOS pass transistor.
5VCC INPUT 3.3V INPUT
2.4V OUTPUT
Initialization
The ISL6529 automatically initializes upon application of input power. Special sequencing of the input supplies is not necessary. The POR function continually monitors the input bias supply voltage at the 5VCC and 12VCC pins. The POR function initiates soft-start operation after these supply voltages exceed their POR threshold voltages.
1.5V OUTPUT
FIGURE 1. ATX SUPPLY POWERING AN ISL6529 EVALUATION BOARD
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Had the cause of the UV still been present after the delay interval, the UV protection circuitry becomes active approximately 875ms into the soft-start interval. A fault signal could then be generated and the outputs once again shut down. The resulting hiccup mode style of protection would continue to repeat indefinitely.
CAPACITOR CURRENT
Output Voltage Selection
1.5V OUTPUT
The output voltage of the PWM converter can be programmed to any level between VIN (i.e. +3.3V) and the internal reference, 0.8V . An external resistor divider is used to scale the output voltage relative to the reference voltage and feed it back to the inverting input of the error amplifier (see Figure 4).
VOUT2 (2.5V)
CAPACITOR CURRENT
VOUT1 (1.5V)
DELAY INTERVAL 1.5V OUTPUT 0V (0.5V/DIV) VOUT2 (2.5V)
INTERNAL SOFT-START FUNCTION
FIGURE 2. TOP SCOPE TRACES ARE VOLTAGE RAMP AND CAPACITOR CURRENT. LOWER TRACES ARE TIME AND VOLTAGE EXPANSION OF UPPER SCOPE TRACES.
DELAY INTERVAL
0V
Undervoltage Protection
The FB and FB2 pins are monitored during converter operation by two separate undervoltage (UV) comparators. If the FB voltage drops below 51.5% of the reference voltage (0.41V), a fault signal is generated. The internal fault logic shuts down both regulators simultaneously when the fault signal triggers a restart. Figure 3 illustrates the protection feature responding to a UV event on VOUT1. At time t0, VOUT1 has dropped below 51.5% of the nominal output voltage. Both outputs are quickly shut down and the internal soft-start function begins producing soft-start ramps. The delay interval, t0 to t3, seen by the output is equivalent to three soft-start cycles. After a short delay interval of 10.5ms, the fourth internal soft-start cycle initiates a normal soft-start ramp of the output, at time t3. Both outputs are brought back into regulation by time t4, as long as the UV event has cleared.
t0
t1
t2 TIME
t3
t4
FIGURE 3. UNDERVOLTAGE PROTECTION RESPONSE
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+12V +5V
To ensure the parallel combination of the feedback resistors meets this criteria, choose a target value for RFB of less than 5k and then apply the following equations:
V OUT2 R5 = ------------------ x R FB V REF R5 x V REF R6 = ---------------------------------------V OUT2 - V REF
12VCC 5VCC +3.3V
(EQ. 3)
VOUT1
+
LOUT
Q1
UGATE
(EQ. 4)
COUT1
Q2
LGATE
ISL6529 ISL6529A
FB R3 R1 C3 C1 C2 COMP
where VOUT2 is the desired linear regulator output voltage and VREF is the internal reference voltage, 0.8V. For an output voltage of 0.8V, simply populate R5 with a value less than 5k and do not populate R6.
Converter Shutdown
Pulling and holding the FB2 pin above a typical threshold of 1.28V will shut down both regulators. Upon release of the FB2 pin, the regulators enter into a soft-start cycle which brings both outputs back into regulation.
R2 R4
FIGURE 4. OUTPUT VOLTAGE SELECTION OF THE PWM
PWM Controller Feedback Compensation
A simplified representation of the voltage-mode control loop used for output regulation by the converter is shown in Figure 6. The output voltage, VOUT, is fed back to the negative input of the error amplifier which is regulated to the reference voltage level, VREF. The error amplifier output, VE/A, is compared with the triangle wave produced by the oscillator, VOSC, to provide a pulse-width modulated (PWM) signal from the PWM comparator. This signal is then used to switch the MOSFET and produce a PWM waveform with an amplitude of VIN at the PHASE node. The square-wave PHASE voltage is then smoothed by the output filter, LOUT and COUT, to produce a DC voltage level. The modulator transfer function is defined as VOUT/VE/A . The internal PWM comparator and driver circuits equate to a DC gain block dominated by the supply voltage, VIN, divided by the peak-to-peak magnitude of the triangle wave, VOSC. The output filter components, LOUT and COUT, shape the overall modulator small-signal transfer function by contributing a double pole break frequency at FLC and a zero at FESR .
However, since the value of R1 affects the values of the rest of the compensation components, it is advisable to keep its value less than 5k. Depending on the value chosen for R1, R4 can be calculated based on the following equation:
R1 x 0.8V R4 = ------------------------------------V OUT1 - 0.8V
(EQ. 1)
If the output voltage desired is 0.8V, simply route VOUT1 back to the FB pin through R1, but do not populate R4. The linear regulator output voltage is also set by means of an external resistor divider as shown in Figure 5. The two resistors used to set the output voltage should not exceed a parallel equivalent value, referred to as RFB, of 5k. This restriction is due to the manner of implementation of the softstart function. The following relationship must be met:
R5 x R6 R FB = --------------------- < 5k R5 + R6
(EQ. 2)
+3.3VIN Q3 R12 VOUT2 + R5 R6 DRIVE2 C4 FB2
COUT2
ISL6529 ISL6529A
R5 V OUT2 = 0.8 x 1 + ------- R6
For frequency compensation considerations set R5 to 4.64k and adjust R6 for the required voltage.
FIGURE 5. OUTPUT VOLTAGE SELECTION OF THE LINEAR
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VIN OSC PWM COMP DRIVER LOUT PHASE +
VOSC
-
VOUT
+
CO
link between the modulator transfer function and a controllable closed loop transfer function of VOUT/VREF. The goal of component selection for the compensation network is to provide a loop gain with high 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees .
ESR (PARASITIC) ZFB ZIN VREF
Compensation Break Frequency Equations
Poles:
1 F P1 = -----------------------------------------------------C1 x C2 2 x R 2 x --------------------- C1 + C2 1 F P2 = ----------------------------------2 x R 3 x C3
VE/A
+ ERROR AMP
(EQ. 8)
(EQ. 9)
DETAILED COMPENSATION COMPONENTS ZFB ZIN C3 R1 R3 VOUT
Zeros:
1 F Z1 = ----------------------------------2 x R 2 x C1 1 F Z2 = -----------------------------------------------------2 x ( R1 + R3 ) x C3
C2 C1 R2
(EQ. 10) (EQ. 11)
COMP
+
FB
Follow this procedure for selecting compensation components by locating the poles and zeros of the compensation network: 1. Set the loop gain (R2/R1) to provide a converter bandwidth of one quarter of the switching frequency. 2. Place the first compensation zero, FZ1, below the output filter double pole (~75% FLC). 3. Position the second compensation zero, FZ2, at the output filter double pole, FLC. (EQ. 5) (EQ. 6) 4. Locate the first compensation pole, FP1, at the output filter ESR zero, FESR. 5. Position the second compensation pole at half the converter switching frequency, FSW. 6. Check gain against error amplifier's open-loop gain. 7. Estimate phase margin; repeat if necessary.
ISL6529
0.8V
FIGURE 6. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN
Modulator Break Frequency Equations
1 F LC = --------------------------------------2 x L O x C O 1 F ESR = ---------------------------------------2 x ESR x C O
The compensation network consists of the error amplifier and the impedance networks ZIN and ZFB . They provide the
INPUT VOLTAGE DRAIN ERROR AMPLIFIER INTERNAL 0.8V REFERENCE + ISL6529 FB C16 C4 DRIVE2 GATE R12 X1 SIMPLIFIED MODEL OF THE MOSFET CGD 1/gfs SOURCE REGULATED OUTPUT R5 CISS = CGS + CGD R6 CGS COUTPUT RSAMPLE ESR RLOAD
FIGURE 7. FIGURE A. SIMPLIFIED DIAGRAM OF THE LINEAR VOLTAGE REGULATOR
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FZ1 100 80 60 GAIN (dB) 40 20 0 -20 -40 -60 COMPENSATION GAIN FZ2 FP1 FP2 OPEN LOOP ERROR AMP GAIN V IN 20 log ----------------- V OSC
Component Considerations
Many unsuspected poles and zeros develop with the selection of external components and operating conditions like output MOSFET transistors, output filter capacitors and load current. These elements will be discussed beginning with the influence of the MOSFET series output resistance, the 1/gfs term shown in Figure 7. At low load currents and low transconductance, the effective output resistance can be as high as several kilohms. The low MOSFET gfs with accompanying high series resistance and large values of output capacitance form a low frequency pole that for many cases becomes the dominate pole in the system and often results in a stable no load system. As the load current is increased, the MOSFET series output resistance is reduced and moves the output pole into a higher frequency region, adding phase shift that can result in a marginally stable or unstable system. Low output capacitor ESR can result in stability problems as mentioned above. In contrast, high output capacitor ESR can improve the system stability. The capacitor and its series resistance function as a zero, often canceling other poles in the loop. Figure 9 shows a system simulation with a 300F, 100m high ESR output capacitor. A single 10pF capacitor from input to output of the error amplifier stabilizes the system for load currents through the 1mA to 3A range.
80 GAIN dB 60 40 20 1mA
55m A
R2 20 log -------- R1
MODULATOR GAIN LOOP GAIN FLC 1K FESR 10K 100K 1M 10M
10
100
FREQUENCY (Hz)
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Figure 8 shows an asymptotic plot of the DC-DC converter's gain vs. frequency. The actual modulator gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown in Figure 8. Using the above procedure should yield a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin.
3A
OUTPUT CAPACITOR 300F, 100m
The linear regulator in the ISL6529 is not internally compensated and therefore allows the user to optimize regulator performance with regard to transient load response. Although the compensation network shown in the application examples in this data sheet provide conservative compensation for a variety of loads, performance can be enhanced with attention to load requirements. Low ESR capacitors can cause stability concerns in discrete IC regulators. Even regulators that are internally compensated can become unstable when these capacitors are placed across their output. There have been suggestions to add series resistance to these capacitors to stabilize the regulator. This approach seems self defeating and throws away a desirable quality.
PHASE DEGREES
Linear Regulator Compensation
0 BODE PLOT OF COMPENSATED REGULATOR AT 3 OUTPUT CURRENTS 0 3A 55mA -50 1mA -100 1mA -150 -200 10 3A 100 1K 100K 10K FREQUENCY (Hz) 1M 10M
FIGURE 9. LOOP RESPONSE WITH ONLY C16 = 10pF COMPENSATION
Contrast this with Figure 10 that shows a Bode plot of simulations of this regulator operating with a 100F, 5m low ESR output capacitor. Note the phase approaching 180 at high current. This is in contrast to the response previously shown with the 300F high ESR capacitor. The 300F output capacitor and its ESR provide phase lead to cancel or offset the pole formed with the MOSFET output resistance and 300F capacitance. Also notice that system stability varies widely with load current. A system can oscillate at no load and be stable at full load, The converse is also possible. Oscillation can also occur at load currents between the current extremes.
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80 GAIN dB 60 40 20 1mA 0 BODE PLOT OF REGULATOR (N0 COMP) AT 3 OUTPUT CURRENTS 0 3A -50 55mA -100 -150 -200 10 100 1mA 1K 100K 10K FREQUENCY (Hz) 1mA 55mA 1M 10M 3A 55mA
the values of R12 and C4 can be adjusted to the frequency where phase lead begins. The second equation shows the upper frequency where phase advance is complete. After capacitor C4 becomes effectively an ac short, the mid band gain is set by the R12/R5 ratio as shown on Figure 11. Several simulations illustrate the compensation with the more difficult 5m, 100F output capacitor. Figure 10 previously showed the Bode plots where the phase response comes dangerously near the oscillatory 180 state at unity gain. A type II network applied across the error amplifier inverting input to the output can be configured to perform this function.
80 GAIN dB 60 40 20 COMPENSATION: C16 = 10pF C4 = 470pF R16 = 200K
The Compensation Network
To provide for system stability with a low ESR output capacitor, where pole cancellation by the capacitor is outside the frequencies of interest, a phase lead network must be used to compensate for the phase lag resulting from MOSFET output resistance and the output capacitor.
PHASE DEGREES
FIGURE 10. LOOP RESPONSE WITH ONLY 100F, 5m OUTPUT CAPACITOR
PHASE DEGREES
1mA 3A 0 BODE PLOT OF REGULATOR (COMP ONLY) AT 3 OUTPUT CURRENTS 0 -50 -100 -150 -200 10 3A 100 1K 100K 10K FREQUENCY (Hz) 1M 10M 54mA 1mA
INTERNAL 0.8V REFERENCE ISL6529 FB C4 REGULATED OUTPUT 80 80
70 60
+ -
DRIVE 2 TO MOSFET
FIGURE 12. LOOP RESPONSE WITH COMPENSATION NETWORK ONLY
R12 C16 80 COMPENSATION: C16 = 10pF C4 = 470pF R16 = 200K 3A
R5
1 ---------------------------------2 R12 C4
GAIN (dB)
1 -------------------------------------------------------- C16 C4 2 R12 ------------------------ C 16 + C 4 R12 20 log ---------R5
GAIN dB PHASE DEGREES
60 40 20
40 60 20 50 0
40
PHASE (DEGREES)
30
0
54mA 1mA 0 BODE PLOT OF COMPENSATED REGULATOR AT 3 OUTPUT CURRENTS 0 3A -50 1mA 54mA -100 135 -150 1mA 3A -200 10M 1M 1K 100K 100 10K 10 FREQUENCY (Hz)
-45 20
10 -90
-135 0 10 10
FIGURE 13. INVERTING INPUT TO OUTPUT GAIN AND PHASE WITH COMPENSATION AND 100F, 5m OUTPUT CAPACITOR
100 100
1,000
1K
10K 100K 10,000 100,000 FREQUENCY (Hz)
1,000,000
1M
10,000,000
10M
FIGURE 11. SCHEMATIC AND BODE PLOT OF COMPENSATION NETWORK
Figure 11 shows the type II compensation network configuration and a simplified straight line representation of the network response. By using the equations in Figure 11,
Figure 12 shows the Bode plot of only the compensation network with the system to illustrate the phase boost in the system. Essentially the phase lead region must be moved to advance the phase where it is close to an oscillatory state. Increasing the value of C4 moves the response lower, aiding the lagging phase at low frequencies and low load current. This operation will reduce phase compensation at higher
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ISL6529, ISL6529A
frequencies and high load current. Figure 13 shows the results of the complete system with output capacitor and compensation network for 45 of phase margin. Because of the large variety of capacitors, varying ESRs and PC board layouts, Table 1, based upon system simulations is provided as a starting point guide to aid in the selection of compensation networks for output capacitors values of 1F, 10F, 100F and 1000F with ESR values of 5m, 30m and 100m for each capacitor value. The frequencies associated with the compensation elements are also shown to aid in component selection. Parallel capacitors of the same value and type can be treated as a combination. For example three 100F, 10m capacitors may be treated as one 300F, 3.3m capacitor. Mixed capacitors require more attention. For example the compensation for a 1000F, low ESR capacitor will suffice for a shunting 10F, low ESR capacitor.
TABLE 1. COMPENSATION NETWORKS FOR LINEAR REGULATOR CAP ESR OUTPUT CAPACITOR DETAIL Comp Network Low Fq Zero (C4 & R12) 5m High Fq Pole (C16 & R12) MidbandGain R12/R5 OUTPUT CAP & ESR Zero Fq Comp Network Low Fq Zero (C4 & R12) 30m High Fq Pole (C16 & R12) Midband Gain R12/R5 OUTPUT Cap & ESR Zero Fq Comp Network Low Fq Zero (C4 & R12) 100m High Fq Pole (C16 & R12) Midband Gain R12/R5 OUTPUT Cap & ESR Zero Fq 1F C16 = 10pF R12 = 47K C4 = 200pF 17kHz 338kHz 20dB 32MHz C16 = 10pF R12 = 47K C4 = 200pF 17kHz 338kHz 20dB 5.3MHz C16 = 10pF R12 = 47K C4 = 200pF 17kHz 338kHz 20dB 1.6MHz 10F C16 = 10pF R12 = 47K C4 = 470pF 7.2kHz 338kHz 20dB 3.2MHz C16 = 10pF R12 = 47K C4 = 470pF 17kHz 338kHz 20dB 530kHz C16 = 10pF R12 = 47K C4 = 470pF 17kHz 338kHz 20dB 160kHz 100F C16 = 10pF R12 = 200K C4 = 470pF 1.7kHz 80kHz 33dB 320kHz C16 = 10pF R12 = 200K C4 = 470pF 1.7kHz 80kHz 33dB 53kHz C16 = 10pF 1000F C16 = 10pF R12 = 470K C4 = 470pF 720Hz 34kHz 40dB 32kHz C16 = 10pF
5.3kHz C16= 10pF
16kHz
1.6kHz
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FN9070.5 April 12, 2005
ISL6529, ISL6529A
The final test for a system is transient load current performance. Ringing or oscillation indicates that the compensation network must be adjusted to assure stable operation with component and environmental variations. Figures 14 and 15 are scope shots that show the regulator with only with a 1500F, 100m capacitor with high frequency ringing with no compensation. A 27pF capacitor, C16 was added in Figure 15. The output step is about 260mV for the 3A load current for an ESR in the order of 90m. After the load current is removed, the output network parasitics ring for about 5s. As an example, consider the turn-off transition of the PWM MOSFET. Prior to turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is picked up by the lower MOSFET and parasitic diode. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes. There are two sets of critical components in a DC-DC converter using the ISL6529, ISL6529A. The switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise. Next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling. A multi-layer printed circuit board is recommended. Figure 16 shows the connections of the critical components in the converter. Note that capacitors CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer, usually a middle layer of the PC board, for a ground plane and make all critical component ground connections through vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminal to the output inductor short. The power plane should support the input and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase node. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the UGATE pin to the MOSFET gate should be kept short and wide enough to easily handle the 1A of drive current. The switching components should be placed close to the ISL6529, ISL6529A first. Minimize the length of the connections between the input capacitors, CIN, and the power switches by placing them nearby. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible. Position the output inductor and output capacitors between the upper MOSFET and lower diode and the load.
OUTPUT VOLTAGE 200mV/DIV
LOAD CURRENT, 1A/DIV
FIGURE 14. 3A TRANSIENT LOAD APPLIED TO THE REGULATOR NO COMPENSATION
OUTPUT VOLTAGE 200mV/DIV
LOAD CURRENT, 1A/DIV
FIGURE 15. 3A TRANSIENT LOAD APPLIED TO THE REGULATOR 27pF COMPENSATION
Application Guidelines
Layout Considerations
Layout is very important in high frequency switching converter design. With power devices switching efficiently at 600kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device over-voltage stress. Careful component layout and printed circuit board design minimizes the voltage spikes in the converters.
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ISL6529, ISL6529A
+3.3 VIN +5 VCC 5VCC GND CBP CIN
PWM Regulator Output Capacitors
Modern digital ICs can produce high transient load slew rates. High frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. The bulk filter capacitor selection is generally determined by the effective series resistance (ESR) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Specialized low-ESR capacitors intended for switchingregulator applications are recommended for the bulk capacitors. The bulk capacitor's ESR determines the output ripple voltage and the initial voltage drop following a high slew-rate transient edge. Aluminum electrolytic, tantalum, and special polymer capacitor ESR values are related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.
+12 VCC 12VCC PGND UGATE CBP Q1
LOUT
VOUT1 LOAD LOAD
ISL6529
LGATE COMP
PHASE Q2 COUT1
C2 R2 FB R4 C3 R3 +3.3 VIN Q3 R5 R6 COUT2 KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER VIA CONNECTION TO GROUND PLANE VOUT2 C1 R1
DRIVE2 FB2
PWM Output Inductor Selection
The PWM converter requires an output inductor. The output inductor is selected to meet the output voltage ripple requirements and sets the converter response time to a load transient. The inductor value determines the converter's ripple current and the ripple voltage is also a function of the ripple current. The ripple voltage and current are approximated by the following equations:
V IN - V OUT V OUT I = ------------------------------- x --------------V IN FS x L V OUT = I x ESR
FIGURE 16. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
The critical small signal components include any bypass capacitors, feedback components, and compensation components. Position the bypass capacitors, CBP, close to the VCC pin with a via directly to the ground plane. Place the PWM converter compensation components close to the FB and COMP pins. The feedback resistors for both regulators should also be located as close as possible to the relevant FB pin with vias tied straight to the ground plane as required.
(EQ. 11)
Component Selection Guidelines
Output Capacitor Selection
Output capacitors are required to filter the output and supply the load transient current. The filtering requirements are a function of switching frequency and output current ripple. The load transient requirements are a function of the transient load current slew rate (di/dt) and magnitude. These requirements are generally met with a mix of capacitors and careful layout.
(EQ. 12)
Increasing the value of inductance reduces the output ripple current and voltage ripple. However, increasing the inductance value will slow the converter response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to slew the inductor current. Given a sufficiently fast control loop design, the ISL6529 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time
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FN9070.5 April 12, 2005
ISL6529, ISL6529A
interval required to slew the inductor current from an initial current value to the final current level. During this interval the difference between the inductor current and the load current must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load:
L O x I TRAN t RISE = ------------------------------V IN - V OUT L O x I TRAN t FALL = -----------------------------V OUT
TRANSISTOR SELECTION/CONSIDERATIONS The ISL6529, ISL6529A require three external transistors. One N-Channel MOSFET is used as the upper switch in a standard buck topology PWM converter. Another MOSFET is used as the lower synchronous switch. The linear controller drives the gate of an N-Channel MOS transistor used as the series pass element. The chosen MOSFET rDS(ON) determines the maximum drop out voltage of the regulator. For all practical purposes, the MOSFET appears as a variable resistor. All he MOSFET transistors should be selected based upon rDS(ON) , gate supply requirements, and thermal management considerations.
(EQ. 13)
Upper MOSFET SWITCH Selection
(EQ. 14) In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses account for a large portion of the power dissipation of the upper MOSFET. Switching losses also contribute to the overall MOSFET power loss.
2 P ConductionUpper I o x r DS ( on ) x D
where ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a +3.3V input source, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time.
(EQ. 15)
1 P Switching -- I o x V IN x t SW x F SW 2
(EQ. 16)
Input Capacitor Selection
The important parameters for the bulk input capacitors are the voltage rating and the RMS current rating. For reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 of the summation of the DC load current. Use a mix of input bypass capacitors to control the voltage overshoot across the switching MOSFETs. Use ceramic capacitance for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. Connect them directly to ground with a via placed very close to the ceramic capacitor footprint. For a through-hole design, several aluminum electrolytic capacitors may be needed. For surface mount designs, tantalum or special polymer capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up.
where Io is the maximum load current, D is the duty cycle of the converter (defined as VO/VIN), tSW is the switching interval, and FSW is the PWM switching frequency. The lower MOSFET has only conduction losses since it switches with zero voltage across the device. Conduction loss is:
2 P ConductionLower I o x r DS ( on ) x ( 1 - D )
(EQ. 17)
These equations assume linear voltage-current transitions and are approximations. The gate-charge losses are dissipated by the ISL6529 and do not heat the MOSFET. However, large gate-charge increases the switching interval, tSW, which increases the upper MOSFET switching losses. Ensure that the MOSFET is within its maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature, air flow, and load current requirements. The gate drive to the switching transistors ranges from slightly below 12V to ground. Because of the large voltage swing, logic-level transistors are not necessary in this application.
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FN9070.5 April 12, 2005
ISL6529, ISL6529A
However, if logic-level transistors or transistors with low VGS(on) are used, close attention to layout guidelines should be exercised, as the low gate threshold could lead to some shoot-through despite counteracting circuitry present aboard the ISL6529. The power dissipated in the linear regulator is:
P LINEAR I O x ( V IN - V OUT )
(EQ. 18)
N-Channel MOSFET Transistor Selection
The main criteria for selection of the linear regulator pass transistor is package selection for efficient removal of heat. Select a package and heatsink that maintains the junction temperature below the rating with a maximum expected ambient temperature.
where IO is the maximum output current and VOUT is the nominal output voltage of the linear regulator.
References
Intersil documents are available on the web at http://www.intersil.com. [1] Technical Brief, Intersil Corporation, TB417, http://www.intersil.com/data/tb/tb417.pdf
ISL6529 Converter Application Circuit
L2 +3.3V C7 1000F 1H C6 470F C8 4.7F
+5V
+12V
C5 1F
C15 1F
Q3 VOUT2 (1A) 2.5V C14 1F
R13 1.0k R5 4.64k C12 1500F R6 2.15k C4 470pF R12 6.8k
5VCC DRIVE2
12VCC
Q1
UGATE
L1 4.7H C9 470F C10 1F
VOUT1 (6A) 1.6V
ISL6529 ISL6529A
FB2 GND
Q2
LGATE COMP FB PGND
C1 47nF R2 10.7k C2 1.2nF R1 1.0k
Q1, Q2 Q3 L1 L2
IRF7313 MTD3055V 919AS-4R7M 919AS-1R0N
IR Fairchild TOKO TOKO
R4 1.0k
R3 10
C3 47nF
FIGURE 17. POWER SUPPLY APPLICATION CIRCUIT FOR A GRAPHICS CONTROLLER
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FN9070.5 April 12, 2005
ISL6529, ISL6529A Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.5x5B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHB ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.35 2.95 2.95 0.28 MIN 0.80 NOMINAL 0.90 0.20 REF 0.33 5.00 BSC 4.75 BSC 3.10 5.00 BSC 4.75 BSC 3.10 0.80 BSC 0.60 16 4 4 0.60 12 0.75 0.15 3.25 3.25 0.40 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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FN9070.5 April 12, 2005
ISL6529, ISL6529A Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574
A1 B C D E

A1 0.10(0.004) C
e
B 0.25(0.010) M C AM BS
e H h L N
0.050 BSC 0.2284 0.0099 0.016 14 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 14 0o 6.20 0.50 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 19
FN9070.5 April 12, 2005

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